The present invention relates to a novel semiconductor device which includes a resistance element.
One type of a nonvolatile memory cell is the MONOS (Metal Oxide Nitride Oxide Substrate) type wherein the gate insulating layer between a channel and a gate is formed of a stacked structure including a silicon oxide layer and a silicon nitride layer, and wherein electric charges are trapped in the silicon nitride layer.
A device shown in FIG. 17 has been known as the nonvolatile memory cell of the MONOS type (disclosed by Y. Hayashi, et al., 2000 Symposium on VLSI Technology, Digest of Technical Papers, page 122 to 123).
In the memory cell 102 of the MONOS type, a word gate 14 is formed over a semiconductor substrate 10 with a first gate insulating layer 12 interposed. A first control gate 20 and a second control gate 30 in the shape of sidewalls are respectively disposed along both the sides of the word gate 14. A second gate insulating layer 22 exists between the bottom of the first control gate 20 and the semiconductor substrate 10, and an insulating layer 24 exists between the side surface of the first control gate 20 and the word gate 14. Likewise, a second gate insulating layer 32 exists between the bottom of the second control gate 30 and the semiconductor substrate 10, and an insulating layer 34 exists between the side surface of the second control gate 30 and the word gate 14. An impurity layer 16 or 18 which constructs a source region or a drain region is formed in that part of the semiconductor substrate 10 which underlies the interval between the opposing control gates 20 and 30 of the memory cells adjacent to each other.
In this manner, one memory cell 102 has two MONOS type memory elements on the sides of the word gate 14. The two MONOS type memory elements can be independently controlled, so that the memory cell 102 can store information of 2 bits.
The operation of the memory cell of the MONOS type is performed as stated below. One control gate of the memory cell 102 can select writing and reading independently of each other by biasing the other control gate to an override voltage.
The writing (programming) will be explained about a case where electrons are injected into the second gate insulating layer (ONO film) 32 at the left of a part CG[i+1] shown in FIG. 17. In this case, the bit line (impurity layer) 18 (D[i+1]) is held biased to a drain voltage of 4 to 5 V. The control gate 30 (CG[i+1]) is biased to 5 to 7 V in order to inject hot electrons into the second gate insulating layer 32 underlying this control gate 30 (CG[i+1]). A word line connected to the word gate 14 (Gw[i] and Gw[i+1]) is biased to a voltage being somewhat higher than the threshold voltage of the word gate, in order to limit a write current to a predetermined value (about 10 μA). The control gate 20 (CG[i]) is biased to the override voltage. Owing to the override voltage, a channel under the control gate 20 (CG[i]) can be rendered conductive irrespective of a storage state. The left bit line 16 (D[i]) is biased to a ground potential. The control gate and impurity layer of the other unselected memory cell are set at the ground potential.
In erasing, stored charges (electrons) are canceled by the injection of hot holes. The hot holes can be created by B—B tunneling in the surface of the bit impurity layer 18. On this occasion, the voltage Vcg of the control gate is biased to a negative voltage (−5 to −6 V), and the voltage of the bit impurity layer to 5 to 6 V.
It is stated in the publication that, according to the above MONOS type memory cell, two programming sites being independently controllable are included within one memory cell, whereupon a bit density of 3F2 can be achieved.
Meanwhile, with the microfabrication of a semiconductor storage device, it is demanded to reduce the area of a resistance element which is included in, for example, the analog IC of the peripheral circuit section of the semiconductor storage device.